Silicon-on-Insulator (SOI) is currently used in applications ranging from supercomputers (like Watson of "Jeopardy" fame) to laptops and game systems, in smart power devices, integrated photonic circuits, and in MEMS. In all these cases, SOI enhances the device performance. The initial driving force for developing SOI material was to increase radiation hardness of integrated circuits. Later, SOI applications entered the mainstream of digital electronics, where they provide increased switching speed of transistors and reduced power consumption. As device gate length is scaled below 50 nm, thin SOI layers are becoming essential to maintain proper transistor action by suppressing the short-channel effects. Eventually, planar transistors will need to be replaced with double gates or with vertical transistors - SOI plays an important role in these novel device architectures as well.
SOI wafer structure is conceptually very simple - a layer of single crystalline silicon that is separated by a layer of amorphous SiO2 from a silicon support or "handle" wafer - however fabrication of such structures requires unique solutions that have challenged materials scientists and engineers for about two decades. This talk will review the evolution of ideas and approaches to forming single crystalline silicon layers on other substrates: heteroepitaxy, epitaxial overgrowth, solid phase epitaxy, porous silicon, and laser recrystallization, and then concentrate on the methods that eventually became dominant. The commercially successful techniques are based on ion implantation applied in unconventional ways. Selected applications of SOI and related engineered substrates will be reviewed.
Prof. George K Celler received his M.Sc. degree in physics from the University of Warsaw and a Ph.D. in solid-state physics from Purdue University. Before joining Rutgers in 2010, he was Chief Scientist at Soitec, where he was responsible for company's technical interactions and collaborations with the US industry and academia in the field of substrate engineering. Before joining Soitec in 2001, he spent 25 years at Bell Laboratories, where he was a Distinguished Member of Technical Staff and Technical Manager. In addition to his long-term interest in silicon-on-insulator structures and their applications, he also investigated laser annealing and rapid thermal processing of semiconductors, and diffusion phenomena in Si and silicon dioxide. He led a large DARPA supported x-ray lithography program at Bell Labs and was a Deputy Manager of X-Ray Lithography Consortium. He published over 200 articles, edited nine books, and was issued 18 US patents. He is a fellow of the American Physical Society and of The Electrochemical Society, and a member of IEEE and MRS. He was a Program Chair and a General Chair of the IEEE-SOI Conference. He has received the 1994 Electronics Division Award of The Electrochemical Society, and two Bell Labs President's Gold Awards. Currently, he is leading a SOI subcommittee of the International Technology Roadmap for Semiconductors (ITRS) and a SOI Standards subcommittee of SEMI, and is a member of the External Advisory Board of the NSF-funded MRSEC at Georgia Tech. on epitaxial graphene. Presently he is exploring heterogeneous integration of compound semiconductors like SiC with silicon by means of ion-assisted crystal cutting and layer transfer.